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1 description the RJ21P3AA0PT is a 1/1.8-type (8.93 mm) solid- state image sensor that consists of pn photo- diodes and ccds (charge-coupled devices). with approximately 3 370 000 pixels (2 152 horizontal x 1 567 vertical), the sensor provides a stable high- resolution color image. features ? optical size : 8.93 mm (aspect ratio 4 : 3) ? interline scan format ? square pixel ? number of image pixels : 2 096 (h) x 1 560 (v) ? number of effective pixels : 2 080 (h) x 1 544 (v) ? number of optical black pixels C horizontal : 2 front and 54 rear C vertical : 5 front and 2 rear ? number of dummy bits C horizontal : 24 C vertical : 2 ? pixel pitch : 3.45 m (h) x 3.45 m (v) ? r, g, and b primary color mosaic filters ? supports monitoring mode ? low fixed-pattern noise and lag ? no burn-in and no image distortion ? blooming suppression structure ? built-in output amplifier ? built-in overflow drain voltage circuit and reset gate voltage circuit ? variable electronic shutter ? package : 20-pin half-pitch dip [plastic] (p-dip020-0500) row space : 12.20 mm pin connections precautions ? the exit pupil position of lens should be 30 to 55 mm from the top surface of the ccd. ? refer to "precautions for ccd area sensors" for details. 3 210 k effective pixels 2 080 1 544 8.93 mm RJ21P3AA0PT RJ21P3AA0PT 1/1.8-type interline color ccd area sensor with 3 370 k pixels 1od 2gnd 3ofd 4pw 5? rs 6nc 1 7nc 2 8? h1 9nc 3 10? h2 20 19 18 17 16 15 14 os gnd nc 5 nc 4 ? v1a ? v1b ? v2 13 ? v3a 12 ? v3b 11 ? v4 20-pin half-pitch wdip top view (p-dip020-0500) in the absence of confirmation by device specification sheets, sharp takes no responsibility for any defects that may occur in equipment using any sharp devices shown in catalogs, data books, etc. contact sharp in order to obtain the latest device specification sheets before using any sharp device. back
2 RJ21P3AA0PT pin description symbol pin name od output transistor drain os output signals ? rs reset transistor clock ? v1a , ? v1b , ? v2 , ? v3a , ? v3b , ? v4 vertical shift register clock ? h1 , ? h2 horizontal shift register clock pw p-well gnd ground nc 1 , nc 2 , nc 3 , nc 4 , nc 5 no connection overflow drain ofd absolute maximum ratings (t a = +25?c) parameter symbol rating unit output transistor drain voltage v od 0 to +18 v reset gate clock voltage v ?rs internal output v vertical shift register clock voltage v ?v v pw to +18 v horizontal shift register clock voltage v ?h C0.3 to +12 v voltage difference between p-well and vertical clock v pw -v ?v C27 to 0 v storage temperature t stg C40 to +85 ?c ambient operating temperature t opr C20 to +70 ?c 2 note notes : 1.do not connect to dc voltage directly. when ofd is connected to gnd, connect v od to gnd. overflow drain clock is applied below 24 vp-p. 2.do not connect to dc voltage directly. when ? rs is connected to gnd, connect v od to gnd. reset gate clock is applied below 8 vp-p. 3.when clock width is below 10 s, and clock duty factor is below 0.1%, voltage difference between vertical clocks will be below 26 v. 1 v internal output v ofd overflow drain voltage 3 v 0 to +18 v ?v -v ?v voltage difference between vertical clocks
3 RJ21P3AA0PT recommended operating conditions parameter symbol min. typ. max. unit note ambient operating temperature t opr 25.0 ?c output transistor drain voltage v od 14.55 15.0 15.45 v notes : 1.use the circuit parameter indicated in "system configuration example" , and do not connect to dc voltage directly. 2.v pw is set below v ?vl that is low level of vertical shift register clock, or is used with the same power supply that is connected to v l of v driver ic. * to apply power, first connect gnd and then turn on v od . after turning on v od , turn on v pw first and then turn on other powers and pulses. do not connect the device to or disconnect it from the plug socket while power is being applied. 1 v 22.8 21.5 20.7 v ?ofd overflow drain clock p-well voltage v pw C8.0 v ?vl v2 ground gnd 0.0 v v C6.65 C7.0 C7.35 v ?v1al , v ?v1bl , v ?v2l v ?v3al , v ?v3bl , v ?v4l vertical shift register clock low level intermediate level high level v ?v1ai , v ?v1bi , v ?v2i v ?v3ai , v ?v3bi , v ?v4i v ?v1ah , v ?v1bh v ?v3ah , v ?v3bh 14.55 0.0 15.0 15.45 v v low level horizontal shift register clock v ?h1l , v ?h2l C0.05 0.0 +0.05 v high level v ?h1h , v ?h2h 4.54.85.5 v 1 v 5.5 4.8 4.5 v ?rs reset gate clock p-p level reset gate clock frequency f ?rs 18.00 mhz horizontal shift register clock frequency f ?h1 , f ?h2 18.00 mhz vertical shift register clock frequency f ?v1a , f ?v1b , f ?v2 f ?v3a , f ?v3b , f ?v4 7.50 khz p-p level
RJ21P3AA0PT 4 characteristics (drive method : 1/30 s frame accumulation) (t a = +25?c, operating conditions : the typical values specified in " recommended operating conditions ". color temperature of light source : 3 200 k, ir cut-off filter (cm-500, 1 mmt) is used.) parameter symbol min. typ. max. unit note standard output voltage v o 150 mv 2 photo response non-uniformity prnu 10 % 3 saturation output voltage v sat 450 530 mv 4 dark output voltage v dark 0.5 3.0 mv 1, 6 dark signal non-uniformity dsnu 0.5 2.0 mv 1, 7 sensitivity (green channel) r (g) 130 160 mv 8 smear ratio smr C90 C82 db 9 image lag ai 1.0 % 10 blooming suppression ratio abl 1 000 11 output transistor drain current i od 4.0 8.0 ma notes : ? within the recommended operating conditions of v od , v ofd of the internal output satisfies with abl larger than 1 000 times exposure of the standard exposure conditions, and v sat larger than 320 mv. 1.t a = +60?c 2.the average output voltage of g signal under uniform illumination. the standard exposure conditions are defined as when vo is 150 mv. 3.the image area is divided into 10 x 10 segments under the standard exposure conditions. each segment's voltage is the average output voltage of all pixels within the segment. prnu is defined by (vmax C vmin)/vo, where vmax and vmin are the maximum and minimum values of each segment's voltage respectively. 4.the image area is divided into 10 x 10 segments. each segment's voltage is the average output voltage of all pixels within the segment. v sat is the minimum segment's voltage under 10 times exposure of the standard exposure conditions. the operation of ofdc is high. (for still image capturing) 5.the image area is divided into 10 x 10 segments. each segment's voltage is the average output voltage of all pixels within the segment. v sat is the minimum segment's voltage under 10 times exposure of the standard exposure conditions. the operation of ofdc is low. 6.the average output voltage under non-exposure conditions. 7.the image area is divided into 10 x 10 segments under non-exposure conditions. dsnu is defined by (vdmax C vdmin), where vdmax and vdmin are the maximum and minimum values of each segment's voltage respectively. 8.the average output voltage of g signal when a 1 000 lux light source with a 90% reflector is imaged by a lens of f4, f50 mm. 9.the sensor is exposed only in the central area of v/10 square with a lens at f4, where v is the vertical image size. smr is defined by the ratio of the output voltage detected during the vertical blanking period to the maximum output voltage in the v/10 square. 10.the sensor is exposed at the exposure level corresponding to the standard conditions. ai is defined by the ratio of the output voltage measured at the 1st field during the non-exposure period to the standard output voltage. 11.the sensor is exposed only in the central area of v/10 square, where v is the vertical image size. abl is defined by the ratio of the exposure at the standard conditions to the exposure at a point where blooming is observed. 5 mv 400 320
RJ21P3AA0PT 5 pixel structure color filter array (1, 1 560) (2 096, 1 560) (1, 1) (2 096, 1) ? v3b ? v1a ? v3b ? v1b ? v3b ? v1b ? v3b ? v1b ? v3a ? v1b ? v3b ? v1b ? v3b ? v1b ? v3b ? v1a ? v3b ? v1b ? v3b ? v1b ? v3b ? v1b ? v3b ? v1b ? v3a ? v1b ? v3b ? v1b ? v3b ? v1b ? v3b ? v1a ? v3b ? v1b ? v3b ? v1b g r g r g r g r g r g r g r g r g r b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r g r pin arrangement of the vertical readout clock 1 pin optical black (5 pixels) optical black (2 pixels) optical black (54 pixels) optical black (2 pixels) 2 096 (h) x 1 560 (v)
RJ21P3AA0PT 6 timing chart notes : 1.do not use these signals immediately after field accumulation mode is transferred to frame accumulation mode for still image capturing. 2.do not use these signals immediately after frame accumulation mode is transferred to field accumulation mode for monitoring image. * start the exposure period after 10 ms later that ofdc is high, and finish before change swept transfer. * apply at least an ofd shutter pulse to ofd in each field accumulation mode. ? v3a ? v2 ? v1b ? v1a vd timing chart example os ofdc ? ofd ? v4 ? v3b 227.5 227.5 227.5 848 227.5 1 pulse diagram in more detail is shown in the figure q to r after next page. field accumulation mode at first frame accumulation mode frame accumulation mode at first field accumulation mode field accumulation mode qwerqq ' qq ' 455 1 455 1 455 1 455 1 q ' (number of vertical line) (at ofd shutter operation) (1, 3, 5, 7, 9 ... ) (2, 4, 6, 8, 10 ... ) (5, 12, 19 ... ) not for use (note 2) (5, 12, 19 .. ) (5, 12, 19 .. ) (5, 12, 19 .. ) frame accumulation mode field accumulation mode not for use (note 1) not for use (note 1) field accumulation mode 848 1
RJ21P3AA0PT 7 os ob3 5 gb rg gb rg gb rg 1531 1545 1559 1524 1538 1552 gb rg gb rg gb rg gb rg gb rg gb rg gb rg 1503 1517 1496 1510 rg gb rg 1475 1489 1482 ? v3a ? v2 ? v3b ? v1b ? v1a hd vd ? ofd ofdc ? v4 q vertical transfer timing ?field accumulation mode? 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 12 26 19 40 54 33 47 68 61 2 640 clk/h ? v3a ? v2 ? v3b os ? v1b ? v1a hd vd ? ofd ofdc ? v4 44444544644744844945045145245345445512345 678910111213141516 1531 1545 1559 1524 1538 1552 5 ob3 12 19 26 33 40 47 54 61 68 1503 1517 1496 1510 gb rg gb rg gb rg gb rg gb rg gb rg gb rg rg gb rg gb rg gb rg gb rg gb 1475 1489 1482 1468 q ' vertical transfer timing ?field accumulation mode? 2 640 clk/h
RJ21P3AA0PT 8 ? v3a ? v2 ? v3b os ? v1b ? v1a hd vd ? ofd ofdc ? v4 451452453454455123456789 61 62 63 64 65 66 67 68 69 70 71 72 73 rg rg rg rg ob2ob41357 not for use w vertical transfer timing ?at first frame accumulation mode? 2 640 clk/h charge swept transfer (2 112 stages) ? ofd ? v3a ofdc ? v4 ? v3b ? v2 ? v1b ? v1a vd hd e vertical transfer timing ?frame accumulation mode? 844845846847848123456789 61 62 63 64 65 66 67 68 69 70 71 72 73 os ob1 ob3 ob5 2 4 6 gb rg rg rg rg rg rg gb gb not for use charge swept transfer (2 112 stages) 1557 1555 1559 1549 1553 1551 2 640 clk/h * do not use the frame signals immediately after field accumulation mode is transferred to frame accumulation mode.
RJ21P3AA0PT 9 ? ofd ? v3a ofdc ? v4 ? v3b ? v2 ? v1b ? v1a vd hd r vertical transfer timing ?at first field accumulation mode? 83783883984084184284384484584684784812345678910111213141516 os gb gb gb gb gb gb gb gb gb gb gb gb gb gb not for use 1534 ob2 1536 1538 1540 1542 1544 1546 1548 1550 1552 1554 1556 1558 1560 2 640 clk/h * do not use the field signals immediately after frame accumulation mode is transferred to field accumulation mode for monitoring image.
RJ21P3AA0PT 10 38.9 s (698 bits) 57.6 s (1 034 bits) (126 bits) (126 bits) 866 ? v3a ? v4 ? v3b ? v2 ? v1a hd 260 222 194 250 166 260 2640 (0) 2640 (0) 908 1160 1034 992 698 824 950 7.02 s 7.02 s ? v1b readout timing ?field accumulation mode? 38.9 s (698 bits) (126 bits) ? v3a ? v3b ? v4 ? v2 ? v1a ? v1b hd 7.02 s readout timing ?frame accumulation mode? w 57.6 s (1 034 bits) (126 bits) ? v3a ? v3b ? v4 ? v2 ? v1a ? v1b hd 7.02 s e 260 222 194 250 166 260 16 16 36 36 2640 (0) 2640 (0) 908 992 698 824 866 950 260 222 194 250 166 260 16 36 36 908 992 866 950 950 1160 1034 2640 (0) 2640 (0)
RJ21P3AA0PT 11 os ? rs ? h2 ? h1 hd horizontal transfer timing ?field accumulation mode?-1 1 clk = 55.7 ns (= 1/18.0 mhz) 2640 (0) 54 82 110 138 166 194 222 250 260 278 28 clk 4-stage transfer 3-stage transfer ofd ? v4 ? v2 ? v1a ? v1b ? v3a ? v3b ? v4 ? v2 ? v1a ? v1b ? v3a ? v3b 152 208 (= 1.56 s) ob (54) 2096 * keep over 1.56 s when vertical transfer clock pulse is overlapping.
RJ21P3AA0PT 12 os ? rs ? h2 ? h1 hd horizontal transfer timing ?field accumulation mode?-2 1 clk = 55.7 ns (= 1/18.0 mhz) 306 278 334 362 390 418 446 474 518 ofd ? v4 ? v2 ? v1a ? v1b ? v3a ? v3b ? v4 ? v2 ? v1a ? v1b ? v3a ? v3b 4-stage transfer 3-stage transfer ob (2) pre scan (24) output (2 096) 1 * keep over 1.56 s when vertical transfer clock pulse is overlapping.
RJ21P3AA0PT 13 os ? rs ? h2 ? h1 hd horizontal transfer timing ?frame accumulation mode?-1 1 clk = 55.7 ns (= 1/18.0 mhz) 2640 (0) 54 82 110 138 166 194 222 250 260 278 ? v4 ofd ? v2 ? v1a ? v1b ? v3a ? v3b 152 208 (= 3.11 s) 56 clk ob (54) 2096 os ? rs ? h2 ? h1 hd horizontal transfer timing ?frame accumulation mode?-2 1 clk = 55.7 ns (= 1/18.0 mhz) 278 306 334 362 390 418 446 474 508 ? v4 ofd ? v2 ? v1a ? v1b ? v3a ? v3b ob (2) pre scan (24) output (2 096) 1 * keep over 3.11 s when vertical transfer clock pulse is overlapping. * keep over 3.11 s when vertical clock pulse is overlapping.
? v1a ? v1b ? v4 ? v3a ? v3b ? v2 hd charge swept transfer timing ?frame accumulation mode? w , e 2h 123 2112 2111 2110 4h 5h 65h 66h 3h 0 260 2640 56 96 176 216 136 56 96 176 216 136 116 76 156 196 116 76 156 196 2616 16 2636 36 2636 36 2616 16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? RJ21P3AA0PT 14 * keep over 1.56 s when vertical transfer clock pulse of charge swept transfer is overlapping.
RJ21P3AA0PT 15 od pw ofd ? v2 ? v1b ? v3a ? v3b ? v4 gnd nc 1 nc 2 ? h1 nc 3 ? h2 os gnd nc 5 nc 4 ? v1a ? rs v 3b v 3a v 1b v 1a v ma v h v 4 v 2 v l v mb pofd nc v h ? h2 vh 1bx v 3x v 2x vh 3bx v 4x v 1x vh 3ax vh 1ax +v dd ofdx ? h1 ? rs v l (v pw ) ccd out v ofdh vh 3bx ofdx v 2x v 1x v 3x v dd gnd v 4x vh 3ax vh 1bx vh 1ax + + 1 2 3 4 5 6 7 8 12 24 23 22 21 20 19 18 17 13 11 14 10 15 9 16 2 3 4 5 6 7 8 19 18 1 20 17 16 15 14 13 9 10 12 11 lr36685 RJ21P3AA0PT (*1) (*1) v od ofdc 270 pf 100 $ 1 m$ 1 m$ 5.6 k$ 47 k$ 47 f 0. 1 f 1.0 f 0.01 f + + 100 k$ 33 k$ be sure to use the parameter indicated in this circuit example. (*1) ? rs , ofd : do not connect to dc voltage directly. system configuration example
RJ21P3AA0PT 16 6.9 0.075 0.4 0.4 6 0.075 0.4 0.4 11.2 0.1 (?2) 12 0.1 20 11 center of effective imaging area and center of package rotation error of die : ? = 1.0? max. (? 1 : effective imaging area) (? 2 : lid's size) 12.2 0.1 refractive index : nd = 1.5 0.5 0.05 (?2) 1.41 0.025 0.25 0.1 12.2 0.04 0.02 0.02 (?1) (?1) a' a a' 20-0.64 typ. 20-0.3 typ. p-1.27 typ. 0.2 m 3.5 0.1 2.4 0.1 2.9 0.1 +0.3 C0 glass lid package ccd 13.8 0.1 13 0.1 (?2) 110 ccd ? a 20 dip (p-dip020-0500) (unit : mm) package outlines
RJ21P3AA0PT 17 precautions for ccd area sensors 1. package breakage in order to prevent the package from being broken, observe the following instructions : 1) the ccd is a precise optical component and the package material is ceramic or plastic. therefore, ? take care not to drop the device when mounting, handling, or transporting. ? avoid giving a shock to the package. especially when leads are fixed to the socket or the circuit board, small shock could break the package more easily than when the package isnt fixed. 2) when applying force for mounting the device or any other purposes, fix the leads between a joint and a stand-off, so that no stress will be given to the jointed part of the lead. in addition, when applying force, do it at a point below the stand-off part. (in the case of ceramic packages) the leads of the package are fixed with low melting point glass, so stress added to a lead could cause a crack in the low melting point glass in the jointed part of the lead. (in the case of plastic packages) C the leads of the package are fixed with package body (plastic), so stress added to a lead could cause a crack in the package body (plastic) in the jointed part of the lead. 3) when mounting the package on the housing, be sure that the package is not bent. C if a bent package is forced into place between a hard plate or the like, the pack- age may be broken. 4) if any damage or breakage occurs on the sur- face of the glass cap, its characteristics could deteriorate. therefore, ? do not hit the glass cap. ? do not give a shock large enough to cause distortion. ? do not scrub or scratch the glass surface. even a soft cloth or applicator, if dry, could cause flaws to scratch the glass. 2. electrostatic damage as compared with general mos-lsi, ccd has lower esd. therefore, take the following antistatic measures when handling the ccd : 1) always discharge static electricity by grounding the human body and the instrument to be used. to ground the human body, provide resistance of about 1 m$ between the human body and the ground to be on the safe side. 2) when directly handling the device with the fingers, hold the part without leads and do not touch any lead. glass cap package lead fixed stand-off fixed lead stand-off low melting point glass
RJ21P3AA0PT 18 3) to avoid generating static electricity, a.do not scrub the glass surface with cloth or plastic. b.do not attach any tape or labels. c.do not clean the glass surface with dust- cleaning tape. 4) when storing or transporting the device, put it in a container of conductive material. 3. dust and contamination dust or contamination on the glass surface could deteriorate the output characteristics or cause a scar. in order to minimize dust or contamination on the glass surface, take the following precautions : 1) handle the ccd in a clean environment such as a cleaned booth. (the cleanliness level should be, if possible, class 1 000 at least.) 2) do not touch the glass surface with the fingers. if dust or contamination gets on the glass surface, the following cleaning method is recommended : ? dust from static electricity should be blown off with an ionized air blower. for anti- electrostatic measures, however, ground all the leads on the device before blowing off the dust. ? the contamination on the glass surface should be wiped off with a clean applicator soaked in isopropyl alcohol. wipe slowly and gently in one direction only. frequently replace the applicator and do not use the same applicator to clean more than one device. ? note : in most cases, dust and contamination are unavoidable, even before the device is first used. it is, therefore, recommended that the above procedures should be taken to wipe out dust and contamination before using the device. 4. other 1) soldering should be manually performed within 5 seconds at 350c maximum at the tip of soldering iron. 2) avoid using or storing the ccd at high tem- perature or high humidity as it is a precise optical component. do not give a mechanical shock to the ccd. 3) * do not expose the device to strong light. for the color device, long exposure to strong light will fade the color of the color filters. * only for color devices

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